Hello all,
Bench rig, CPU 1214C, TIA V17, learning about cycle time with a trace. OB1 calls FC_Sequence, which uses a bit Part_Present to start a small timer and an output, and FC_Sensors, which sets Part_Present from the input I0.0.
The trace shows the output reacting one cycle after the input goes on, about 2 to 3 ms later, every single time. I was expecting it in the same cycle.
I moved both calls out of OB1 into OB30 at 1 ms, same order, thinking faster would sort it, and the lag got smaller in ms but it's still one cycle behind. A different input does exactly the same thing.
Is this normal? Could anyone explain why it happens, I'd rather understand it than just make it go away.
V17, noted. Which order are the two calls in OB1, network 1 and network 2? Post the network list, I think I know before you answer.
Network 1: CALL FC_Sequence. Network 2: CALL FC_Sensors. Sensors last, because I wrote it last. Screenshot of OB1 attached.
There's your cycle. OB1 runs top to bottom, once per cycle. Network 1 reads Part_Present as the previous cycle left it. Network 2 then sets it. The new value waits until the next cycle reaches network 1 again. Producer after consumer, one cycle of delay, every time, on every PLC ever made, on the 300 with OB1 and on a Logix with rung order.
Swap them. FC_Sensors in network 1, FC_Sequence in network 2, and the delay's gone.
OB30 at 1 ms didn't fix it because the order inside was the same, it only made the cycle shorter, so one cycle of lag got shorter with it. There's a writeup on the cycle here: https://plctr.com/understanding-plc-scan-time-and-cycle-time/
Swapped the two calls over. Trace shows the output in the same cycle as the input now, screenshot attached.
It was the call order all along. The bit was written at the bottom of OB1 and read at the top, so the top only ever saw what the previous cycle had left behind. FC_Sensors in network 1, FC_Sequence in network 2, delay gone.
I get it now, but there's one thing left. Even after the swap there's still about 1 ms between the input edge and the output on the trace. That'll be the process image, inputs read at the start and outputs written at the end? Thanks sergio74 and sanjay12.
Yes, the process image. Confirm the trace tomorrow and I'd call it closed.